8 Datasheet, Volume 1
Tables
1-1 PCIe Supported Configurations in Mobile Products .......................................................14
1-2 Related Documents.................................................................................................21
2-1 Supported SO-DIMM Module Configurations 1,2 ..........................................................23
2-2 DDR3 System Memory Timing Support ......................................................................24
2-3 Reference Clock......................................................................................................36
4-1 System States........................................................................................................45
4-2 Processor Core/Package State Support ......................................................................45
4-3 Integrated Memory Controller States.........................................................................46
4-4 PCIe Link States .....................................................................................................46
4-5 DMI States ............................................................................................................46
4-6 Processor Graphics Controller States .........................................................................46
4-7 G, S, and C State Combinations................................................................................47
4-8 D, S, and C State Combination .................................................................................47
4-9 Coordination of Thread Power States at the Core Level ................................................50
4-10 P_LVLx to MWAIT Conversion ...................................................................................50
4-11 Coordination of Core Power States at the Package Level ..............................................53
4-12 Targeted Memory State Conditions............................................................................58
5-1 TDP Specifications ..................................................................................................67
5-2 Junction Temperature Specification ...........................................................................67
5-3 Package Turbo Parameters.......................................................................................68
5-4 Idle Power Specifications .........................................................................................69
6-1 Signal Description Buffer Types ................................................................................77
6-2 Memory Channel A..................................................................................................78
6-3 Memory Channel B..................................................................................................79
6-4 Memory Reference and Compensation .......................................................................79
6-5 Reset and Miscellaneous Signals ...............................................................................80
6-6 PCI Express* Graphics Interface Signals ....................................................................80
6-7 Embedded Display Port Signals.................................................................................81
6-8 Intel® Flexible Display Interface...............................................................................81
6-9 DMI - Processor to PCH Serial Interface .....................................................................81
6-10 PLL Signals ............................................................................................................82
6-11 TAP Signals............................................................................................................82
6-12 Error and Thermal Protection....................................................................................83
6-13 Power Sequencing ..................................................................................................83
6-14 Processor Power Signals ..........................................................................................84
6-15 Sense Pins.............................................................................................................84
6-16 Ground and NCTF ...................................................................................................85
6-17 Future Compatibility................................................................................................85
6-18 Processor Internal Pull Up/Pull Down .........................................................................85
7-1 IMVP7 Voltage Identification Definition ......................................................................89
7-2 VCCSA_VID configuration ........................................................................................92
7-3 Signal Groups1.......................................................................................................93
7-4 Storage Condition Ratings........................................................................................96
7-5 Processor Core (VCC) Active and Idle Mode DC Voltage and Current Specifications ..........97
7-6 Processor Uncore (VCCIO) Supply DC Voltage and Current Specifications .......................98
7-7 Memory Controller (VDDQ) Supply DC Voltage and Current Specifications ......................99
7-8 System Agent (VCCSA) Supply DC Voltage and Current Specifications ...........................99
7-9 Processor PLL (VCCPLL) Supply DC Voltage and Current Specifications...........................99
7-10 Processor Graphics (VAXG) Supply DC Voltage and Current Specifications .................... 100
7-11 DDR3 Signal Group DC Specifications ...................................................................... 101
7-12 Control Sideband and TAP Signal Group DC Specifications .......................................... 102
7-13 PCI Express DC Specifications ................................................................................102
7-14 eDP DC Specifications ...........................................................................................103