Intel 2ND GENERATION INTEL CORE PROCESSOR FAMILY MOBILE - DATASHEET VOLUME 1 01-2011 - Page 94

Electrical Specifications
94 Datasheet, Volume 1
Single Ended
Asynchronous
CMOS/Open Drain Bi-
directional
PROCHOT#
Single Ended
Asynchronous CMOS
Output
THERMTRIP#, CATERR#
Single Ended
Asynchronous CMOS
Input
SM_DRAMPWROK, UNCOREPWRGOOD
4
,
PM_SYNC, RESET#
Single Ended
Asynchronous Bi-
directional
PECI
Voltage Regulator
Single Ended CMOS Input VIDALERT#
Single Ended Open Drain Output VIDSCLK
Single Ended CMOS Output VCCSA_VID[1]
Single Ended
Bi-directional CMOS
Input/Open Drain
Output
VIDSOUT
Single Ended Analog Output
VCCSA_SENSE
VCC_DIE_SENSE
Differential Analog Output
VCC_SENSE, VSS_SENSE
VCCIO_SENSE, VSS_SENSE_VCCIO
VAXG_SENSE, VSSAXG_SENSE
VCC_VAL_SENSE, VSS_VAL_SENSE
VAXG_VAL_SENSE, VSSAXG_VAL_SENSE
Power/Ground/Other
Single Ended
Power
V
CC
, V
CCIO
, V
CCSA
, V
CCPLL
, V
DDQ
, V
AXG,
V
CCPQE
3
,
V
CCDQ
3
Ground V
SS
, V
SS_NCTF
3
,
DC_TEST_xx#
No Connect RSVD, RSVD_NCTF
Tes t Po in t RS VD _T P
Other SKTOCC#, PROC_DETECT#
3
PCI Express* Graphics
Differential PCI Express Input PEG_RX[15:0], PEG_RX#[15:0]
Differential PCI Express Output PEG_TX[15:0], PEG_TX#[15:0]
Single Ended Analog Input PEG_ICOMPO, PEG_ICOMPI, PEG_RCOMPO
eDP
Differential eDP Output eDP_TX[3:0], eDP_TX#[3:0]
Differential eDP Bi-directional eDP_AUX, eDP_AUX#
Single Ended
Asynchronous CMOS
Input
eDP_HPD
Single Ended Analog Input eDP_ICOMPO, eDP_COMPIO
DMI
Differential DMI Input DMI_RX[3:0], DMI_RX#[3:0]
Differential DMI Output DMI_TX[3:0], DMI_TX#[3:0]
Intel
®
FDI
Single Ended CMOS Input
FDI0_FSYNC, FDI1_FSYNC, FDI0_LSYNC,
FDI1_LSYNC
Table 7-3. Signal Groups
1
(Sheet 2 of 3)
Signal Group Type Signals