Chapter
1. Assembly
language
and
Processors
1-8
8080
IACCUMULATORI
FLAGS
I
8085
HIGH
LOW
I
I I
I
!
I
B
C STACK POINTER
INSTRUCTION
DECODER
I
D
I
E
I
I
PROGRAM
1
COUNTER
i
Y DATA
BUS
LATCH
I
H
I
L
I
I
ADDRESS
:
BUS
LATCH
I
•
ROM
RAM
Figure 1-4. I nstruction Fetch
The processor initiates the instruction fetch
by
latching the contents
of
the program counter on the address bus,
and then increments the program counter
by
one to indicate the address
of
the next instruction byte.
When
the
memory responds, the instruction
is
decoded into the series
of
actions shown
in
Figure 1-5.
NOTE
The following description
of
the execution of the
MOV
M
,C
instl·uction
is
conceptually correct, but
does not
aCCOL
nt for normal bus control. For details
concerning memory interface, refer to the User's
Manual for your processor.
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