Chapter
1.
Assembly
Language
and
Processors
8085
PROCESSOR
DIFFERENCES
The differences between the
8080
proces'>or and the
8085
processor will be
mme
obviou,> to the system designer
than
to
the programmer. Except for two additional instructions, the
8085
in'>truction set
is
identical to and fully
compatihle with the
8080
instruction
'>et.
Mo,;t
programs written for the
8080
should
operate
on the
8085
with-
out
modification. The only programs that may require changes arc those with critical timing routines; the higher
system
<;peed
of
the
8085
may alter the time values
of
,>uch
routines.
A
partial listing
of
8085
de,ign fcature,> includes the following:
• A ,ingll' 5 volt power ,uppl),.
•
Execution speed, ap.PI-oximately 50%
fa,ter
than the 8080.
• Incorporation
in
the
proce'><;()1
of
the featurc<;
of
the
8224
Clock
Geneldtor
and Driver and the
8228
Sy,tem
Controller and
Bu'>
Drivel-.
• A non·maskable
TRAP
interrupt
fOl"
h,mdling serious problems such
as
power
failul-e'>.
• Three separately maskablc interrupt<,
that
gcnel-ate internal RST
imtructions.
•
Input/output
line, for serial data transfer.
Programming for the
8085
1-24
For the programmer, the new
featLlI-es
of the 8085 all' summ,niLed
in
the two new instructions
SIM
and RIM.
These instructions differ from 'the
8080
instr JctioJl',
in
that each has multiple function'>. The
SIM
in<,lruction
sets the
interrupt
mask and/O! writes
out
a bit
of
serial delta. The proglammCl" must place the desiled
interrupt
mask
and/or
scrial
output
in
the dccumulatClI prior to
execution
of
the
SIM
instruction. The
RIM
imtruction
reads a bit
of
serial data if one
is
present a
III
I the
interrupt
ma<;k
into the accumuLitor. Details
of
these instruc-
tions arc covered
in
Chapter 3.
Despite the new
interl-upt features
of
the 80B5, programming for
intenupts
i.,
little ch,mged. Notice, however,
that
8085 hardware
interrupt
RESTART addre,<;e,
fall
hetween the existing
8080
REST ART addresses. Therefore,
only four bytes arc available for certain RST instruction'>.
AI<;o,
the
TRAP
interrupt
input
i, non-maskable and
cannot
be
di,ahled. If your application usc, his input, he certdin to plw:ide
,iI)
intclTupt
routine
for it.
The
interrupt<; have the following priority:
TRAP
RSn.5
RST6.5
RST5.5
INTR
higheq
lowe'>t
When more than one
interrupt
is
pending, the processor always recognizes the higher priority
interrupt
first.
These priorities
apply only to the ,>equence
in
which
interrupts
arc recogni/ed. Program
routines
that
service
interrupts
have no special priority. Thus, an RST5.5
interrupt
can interl-upt the service
routine
for an RST7.5
interrupt.
If
you
want
to
protect
a service routine from
interruption,
either disable the
interrupt
system
(DI
instruction)'
or mask
out
other
potential
interrupts
(SIM
instruction).
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