Chapter
3. Instruction Set
HLT
IN
3-24
zero. A
common
instruction sequence at this point
is
EI,
HL
T. These instructions enable
the
interrupt
system
(RESET
also disables the
interrupt
system) and halt the processor. A subsequent manual or automatic
interrupt
then determines the effective start-up address.
HALT
The
HL
T instruction halts
tht~
processor. The program
counter
contains the address
of
the next sequential
instruction. Otherwise, the
flags and registers remain unchanged.
[~
0
13
Cycles:
States: 7
(5
on
8085)
Flags: none
Once
in
the halt state, the processor can
be
restarted only by
an
external event, typically
an
interrupt. Therefore,
you should
be
certain
that
interrupts are enabled before the
HL
T in'>truction
i'>
executed. See the description
of
the
EI
(Enable Interrupt) instruction.
If an
8080
HL
T instruction
is
executed while interrupts are disabled, the only way to restart the processor i,
by application
of
a RESET
'>ignal.
This forces the program
counter
to zero. The same
is
true
of
the
8085,
except
for the
TRAP
interrupt,
which
i'i
recognized even when the interrupt system
is
disabled.
The processor can temporarily Icave the halt state to service a direct memory access request. However, the pro·
cessor reenters the halt state once the request has been serviced.
A basic
purpo,>e for the
HL
T instruction
is
to allow
the
processor to pause while waiting for an interrupt from a
peripheral device. However, a halt wastes processor resources dnd should
be
used only when there
i'>
no useful
processing
task dVdilable.
INPUT FROM PORT
The
IN
instruction
read'>
eight
bit'>
of
data from the specified port and
load,>
it
into the dccumulator.
NOTE
This description
is
restricted to the exact function
of
the
IN
in'>truction.
Input/output
structures are described
in
the 8080 or 8085 Microcomputer
Systems User's Manual.
Opcode Operand
IN
exp
The operand expression may
be
a number or any expression
that
yield,>
d value
in
the range
OOH
through OFFH.
To Next Page
Loading...
