Chapter
T.
Assembly
Language
and
Processors
Instructions
that
include a direct address require three bytes of storage: one for the instruction code, and two
for the
16·bit address.
Register Indirect Addressing. Register indirect instructions reference memory
via
a register pair. Thus, the
instruction
MOV
M,C
moves the contents
of
the C register into the memory address stored
in
the
Hand
L
register pair. The instruction LDAX B
load, the accumulator with the byte
of
data specified
by
the address
in
the
Band
C register pair.
Combined Addressing Modes. Some instructions use a combination
of
addressing modes. A CALL instruction,
for example, combines direct addressing and register indirect addressing. The direct address
in
a CALL instruction
specifies the address of the desired subroutine; the register indirect address
is
the stack pointer. The CALL
instruction pushes the current contents
of
the program counter into the memory location specified
by
the stack
pointer.
Timing
Effects
of
Addressing Modes. Addressing modes affect both the amount of time required for executing
an instruction and the
amount
of
memory required for its storage. For example, instructions
that
use
implied or
register addressing execute very quickly since they deal directly with the processor hardware or with data already
present
in
hardware registers. More important, however,
is
that the entire instruction can
be
fetched with a
single memory access. The number of memory accesses required
is
the single greatest factor
in
determining
execution timing. More memory accesses require more execution time. A
CALL instruction, for example, requires
five
memory accesses: three to access the entire instruction, and two more to push the contents of the program
counter
onto
the stack.
The processor can access memory once
during each processor cycle. Each cycle comprises a variable number
of
states. (The individual instruction descriptions
in
Chapter 3 specify the number of cycles and states required for
each instruction.) The length
of
a state depends on the clock frequency specified for your system, and may
range from
480
nanoseconds to 2 microseconds. Thus, the timing
of
a four state instruction may range from
1.920 microseconds through 8 microseconds. (The 8085 has a maximum clock frequency of
320
nanoseconds
and therefore
can execute instructions
aboJt
50%
faster-
than the 8080.)
Instruction Naming Conventions
The mnemonics assigned to the instructions are
~esigned
to indicate the function
of
the instruction. The instruc-
tions
fall
into the following functional categories:
Data Transfer Group. The data transfer instructions move data between registers or between memory and
registers.
MOV
MVI
LOA
STA
LHLD
SHLD
Move
Move
Immediate
Load Accumulator Directly from Memory
Store Accumulator Directly
in
Memory
Load
Hand
L Registers Directly from Memory
Store
Hand
L Registers Directly
in
Memory
ALL
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