Intel BX80623I32100

6 Datasheet, Volume 1
7.11.3 Input Device Hysteresis ...........................................................................87
8 Processor Pin and Signal Information ......................................................................89
8.1 Processor Pin Assignments ..................................................................................89
9 DDR Data Swizzling................................................................................................ 109
Figures
1-1 Desktop Platform System Block Diagram Example .......................................................10
2-1 Intel
®
Flex Memory Technology Operation ..................................................................22
2-2 PCI Express* Layering Diagram.................................................................................24
2-3 Packet Flow through the Layers.................................................................................25
2-4 PCI Express* Related Register Structures in the Processor ............................................26
2-5 PCI Express* Typical Operation 16 lanes Mapping........................................................27
2-6 Processor Graphics Controller Unit Block Diagram ........................................................28
2-7 Processor Display Block Diagram ...............................................................................31
4-1 Power States ..........................................................................................................43
4-2 Idle Power Management Breakdown of the Processor Cores ..........................................47
4-3 Thread and Core C-State Entry and Exit .....................................................................47
4-4 Package C-State Entry and Exit.................................................................................51
7-1 Example for PECI Host-clients Connection...................................................................86
7-2 Input Device Hysteresis ...........................................................................................87
8-1 Socket Pinmap (Top View, Upper-Left Quadrant) .........................................................90
8-2 Socket Pinmap (Top View, Upper-Right Quadrant) .......................................................91
8-3 Socket Pinmap (Top View, Lower-Left Quadrant) .........................................................92
8-4 Socket Pinmap (Top View, Lower-Right Quadrant) .......................................................93
Tables
1-1 PCI Express* Supported Configurations in Desktop Products .........................................12
1-2 Terminology ...........................................................................................................16
1-3 Related Documents .................................................................................................18
2-1 Supported UDIMM Module Configurations ...................................................................20
2-2 Supported SO-DIMM Module Configurations (AIO Only) ................................................20
2-3 DDR3 System Memory Timing Support.......................................................................21
2-4 Reference Clock ......................................................................................................33
4-1 System States ........................................................................................................44
4-2 Processor Core / Package State Support.....................................................................44
4-3 Integrated Memory Controller States .........................................................................44
4-4 PCI Express* Link States..........................................................................................44
4-5 Direct Media Interface (DMI) States...........................................................................45
4-6 Processor Graphics Controller States..........................................................................45
4-7 G, S, and C State Combinations ................................................................................45
4-8 Coordination of Thread Power States at the Core Level.................................................47
4-9 P_LVLx to MWAIT Conversion....................................................................................48
4-10 Coordination of Core Power States at the Package Level ...............................................50
6-1 Signal Description Buffer Types .................................................................................61
6-2 Memory Channel A Signals .......................................................................................62
6-3 Memory Channel B Signals .......................................................................................63
6-4 Memory Reference and Compensation........................................................................63
6-5 Reset and Miscellaneous Signals................................................................................64
6-6 PCI Express* Graphics Interface Signals.....................................................................65
6-7 Intel
®
Flexible Display Interface (Intel
®
FDI) ..............................................................65
6-8 Direct Media Interface (DMI) Signals – Processor to PCH Serial Interface ........................66
6-9 Phase Lock Loop (PLL) Signals ..................................................................................66
6-10 Test Access Points (TAP) Signals ...............................................................................66