Datasheet, Volume 1 7
6-11 Error and Thermal Protection Signals......................................................................... 67
6-12 Power Sequencing Signals........................................................................................ 67
6-13 Processor Power Signals .......................................................................................... 68
6-14 Sense Signals......................................................................................................... 68
6-15 Ground and Non-Critical to Function (NCTF) Signals .................................................... 68
6-16 Processor Internal Pull-Up / Pull-Down Resistors ......................................................... 69
7-1 VR 12.0 Voltage Identification Definition .................................................................... 73
7-2 VCCSA_VID configuration ........................................................................................ 76
7-3 Signal Groups 1...................................................................................................... 77
7-4 Storage Condition Ratings........................................................................................ 79
7-5 Processor Core Active and Idle Mode DC Voltage and Current Specifications.................... 80
7-6 Processor System Agent I/O Buffer Supply DC Voltage and Current Specifications ........... 82
7-7 Processor Graphics VID based (V
AXG
) Supply DC Voltage and Current Specifications ........ 83
7-8 DDR3 Signal Group DC Specifications ........................................................................ 84
7-9 Control Sideband and TAP Signal Group DC Specifications ............................................ 85
7-10 PCI Express* DC Specifications................................................................................. 85
7-11 PECI DC Electrical Limits.......................................................................................... 87
8-1 Processor Pin List by Pin Name ................................................................................. 94
9-1 DDR Data Swizzling Table – Channel A .................................................................... 110
9-2 DDR Data Swizzling Table – Channel B .................................................................... 111
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