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Intel D850MVSE - Page 49

Intel D850MVSE
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Technical Reference
49
Table 14. I/O Map (continued)
Address (hex) Description
8 bytes on an 8-byte boundary
(Note 4)
OHCI controller
96 contiguous bytes starting on a 128-byte
divisible boundary
ICH2 (ACPI + TCO)
64 contiguous bytes starting on a 64-byte
divisible boundary
D850MD/D850MV board resource
64 contiguous bytes starting on a 64-byte
divisible boundary
Onboard audio controller
32 contiguous bytes starting on a 32-byte
divisible boundary
(Note 5)
ICH2 (USB controller 1)
16 contiguous bytes starting on a 16-byte
divisible boundary
ICH2 (SMBus)
4096 contiguous bytes starting on a 4096-byte
divisible boundary
Intel 82801BA PCI bridge
256 contiguous bytes starting on a 256-byte
divisible boundary
ICH2 audio mixer
64 contiguous bytes starting on a 64-byte
divisible boundary
ICH2 audio bus mixer
256 contiguous bytes starting on a 256-byte
divisible boundary
ICH2 modem mixer
32 contiguous bytes starting on a 32-byte
divisible boundary
(Note 5)
ICH2 (USB controller 2)
96 contiguous bytes starting on a 128-byte
divisible boundary
(Note 5)
LPC47M142
96 contiguous bytes starting on a 128-byte
divisible boundary
(Note 4)
LPC47M132
Notes:
1. Default, but can be changed to another address range
2. Dword access only
3. Byte access only
4. USB 2.0 option only
5. USB 1.1 option only
NOTE
Some additional I/O addresses are not available due to ICH2 address aliassing.
For information about Refer to
ICH2 addressing Section 1.3, page 18

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