Intel P8700 - Core 2 Duo Processor Datasheet

Low Power Features
12 Datasheet
Figure 1. Core Low-Power States
C2
†
C0
Stop
Grant
Core state
break
P_LVL2 or
MWAIT(C2)
C3
†
Core
state
break
P_LVL3 or
MWAIT(C3)
C1/MWAIT
Core state
break
MWAIT(C1)
C1/Auto
Halt
Halt break
HLT instruction
C4
† ‡
/C6
Core State
break
P_LVL4 or
P_LVL5/P_LVL6
ø
MWAIT(C4/C6)
STPCLK#
deasserted
STPCLK#
asserted
STPCLK#
deasserted
STPCLK#
asserted
STPCLK#
deasserted
STPCLK#
asserted
halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt
core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted)
† — STPCLK# assertion and de-assertion have no effect if a core is in C2, C3, or C4.
‡ — Core C4 state supports the package level Deep C4 sub-state.
Ø — P_LVL5/P_LVL6 read is issued once the L2 cache is reduced to zero.

Intel P8700 - Core 2 Duo Processor Specifications

General

Processor Number	P8700
Number of Cores	2
Threads	2
Clock Speed	2.53 GHz
Cache	3 MB L2 Cache
Bus Speed	1066 MHz
TDP	25 W
Lithography	45 nm
Socket	PGA478
Instruction Set	64-bit
Max Memory Size	8 GB
Max Memory Channels	2
Max Memory Bandwidth	17.1 GB/s
Thermal Monitoring Technologies	Yes
Execute Disable Bit	Yes
Idle States	Yes
Enhanced Intel SpeedStep Technology	Yes
Package Size	35mm x 35mm
Intel 64	Yes
Intel Trusted Execution Technology	No
AES New Instructions	No
Virtualization Technology	VT-x
Memory Types	DDR3