Low Power Features
18 Datasheet
2.1.2.6.3 Dynamic Cache Sizing
Dynamic Cache Sizing allows the processor to flush and disable a programmable
number of L2 cache ways upon each Deeper Sleep entry under the following
conditions:
• The second core is already in C4 and Intel Enhanced Deeper Sleep state or Deep
Power Down Technology state (C6) is enabled (as specified in Section 2.1.1.6).
• The C0 timer that tracks continuous residency in the Normal package state has not
expired. This timer is cleared during the first entry into Deeper Sleep to allow
consecutive Deeper Sleep entries to shrink the L2 cache as needed.
• The FSB speed to processor core speed ratio is below the predefined L2 shrink
threshold.
The number of L2 cache ways disabled upon each Deeper Sleep entry is configured in
the BBL_CR_CTL3 MSR. The C0 timer is referenced through the
CLOCK_CORE_CST_CONTROL_STT MSR. The shrink threshold under which the L2
cache size is reduced is configured in the PMG_CST_CONFIG_CONTROL MSR. If the
FSB speed to processor core speed ratio is above the predefined L2 shrink threshold,
then L2 cache expansion will be requested. If the ratio is zero, then the ratio will not be
taken into account for Dynamic Cache Sizing decisions.
Upon STPCLK# deassertion, the first core exiting Intel Enhanced Deeper Sleep state or
Deep Power Down Technology state will expand the L2 cache to two ways and
invalidate previously disabled cache ways. If the L2 cache reduction conditions stated
above still exist when the last core returns to C4 and the package enters Intel
Enhanced Deeper Sleep state or Deep Power Down Technology state (C6), then the L2
will be shrunk to zero again. If a core requests a processor performance state resulting
in a higher ratio than the predefined L2 shrink threshold, the C0 timer expires, or the
second core (not the one currently entering the interrupt routine) requests the C1, C2,
or C3 states, then the whole L2 will be expanded upon the next interrupt event.
In addition, the processor supports Full Shrink on L2 cache. When the MWAIT Deep
Power Down Technology state instruction is executed with a hint=0x2 in ECX[3:0], the
micro code will shrink all the active ways of the L2 cache in one step. This ensures that
the package enters Deep Power Down Technology immediately when both cores are in
CC6 instead of iterating till the cache is reduced to zero. The operating system (OS) is
expected to use this hint when it wants to enter the lowest power state and can
tolerate the longer entry latency.
L2 cache shrink prevention may be enabled as needed on occasion through an
MWAIT(C4) sub-state field. If shrink prevention is enabled, the processor does not
enter Intel Enhanced Deeper Sleep state or Intel Deep Power Down state since the L2
cache remains valid and in full size.
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