SECTION 7
Principles of Operation
7.1 INTRODUCTION
This section contains an overall functional description of
the Model 263 in block diagram form as well as details of
the various sections of the instrument. Information con-
cerning the voltage source, ohms source, current sources
and charge sources is included.
Information is arranged to provide a description of each
of the functional blocks within the instrument. Many of
these descriptions include simplified schematics and block
diagrams. Detailed schematic diagrams and component
layout drawings for the various circuit boards are located
at the end of Section 9.
7.2 OVERALL FUNCTIONAL DESCRIPTION
A simplified block diagram of the Model 263 is shown in
Figure 7-l. The voltage source is comprised of a D/A con-
verter and an inverting ranging amplifier. The D/A con-
verter uses the pulse width modulation (PWM) method
where the duty cycle of a square wave is filtered to obtain
a DC value. The DC output of the PWM is then properly
conditioned by the ranging amplifier and routed to the
OUTPUT connector or to the current and charge circuitry.
OHMS sourcing is a simple matter of switch selecting the
approprite range resistors and connecting them to the
output.
Both current sources (AMPS and AMPS V/R) use the
voltage and the OHMS range resistors to genemte current.
The AMPS V/R function sources current by placing a range
resistor in series with the voltage source, while the AMPS
function uses an electrometer amplifier to generate current.
The digital section is based upon the 146805E2 CMOS
microprocessor. It performs the tasks of programming the
A/D converter, controlling the configuration of the voltage
source ranging amplifier, displaying data, and com-
municating over the IEEE-488 bus.
7.3 VOLTAGE SOURCE
Refer to the mother board schematic (263-106, sheet 2) for
the following discussion on the voltage source. A block
diagram of the voltage source is shown in Figure 7-2.
The heart of the voltage source is the 16-bit pulse width
modulated (PWM) digital-to-analog converter (D/A). This
type of D/A derives the DC output by varying the the du-
ty cycle of a square wave and then filtering it. Figure 7-3
shows PWM waveforms that have a duty of cycle of 1:2
and 1:lO. Filtering waveform A results in a DC value of %
of the peak voltage. Filtering waveform B results in a DC
due of l/lo of the peak voltage.
The PWM output is generated by U9 and UlO (S-bit
shift/store registers), U7 and U8 (magnitude comparators),
Ul.2 and UW (binary counters), and LJ20 (NAND gates).
Counters Ul2 and Ul3 are cascaded to provide one 16-bit
counter. This counter is driven by loMHz crystal Yl to pro-
vide a fundamental PWM output frequency of l52.59Hz.
The comparator outputs of U7 and U8 are gated by U20
to obtain the PWM output. The PWM output is then
sychronized with the clock at U5 (D-type flip-flop). The
svnchronized outuuts of U5
(pins
8 and 9) are then buf-
fered by U6 (MOSFET driverrthat provides level shifting
and the drive needed to switch 42 and 43 (N-channel
MOSPOW FETs)
FETs Q2 and Q3 switch between an accurate, stable
reference voltage ( - 10.6V) and signal common providing
the accurate pulse width modulated signal. The output of
42 and 43 is filtered by the 3-pole active filter comprised
of U3, R32, R33, R34, C28, C29 and C30 (see Figure 7-4).
This filter provides 8OdB of filtering at the fundamental
frequency of the PWM signal. The filtered output is then
applied to a low noise, low offset voltage inverting
amplifier that has selectable gains of x2 (2OV range), t5
(2V range) and t50 (2OOmV range).
7-l
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