10 Keysight Agile Signal Generator Service Guide
Troubleshooting
A5 Infrastructure Board
The Infrastructure Board provides the following functions:
— Connection between the CPU Carrier Board and Mother Board
— Local power supplies from +12VDC for Infrastructure Board and CPU Carrier
Board
— CPU Power OK signal to CPU for booting process
— PCI Express distribution from CPU host to Rear Panel, DAC Board, RF Deck
Interface and Reference Board endpoints
— PCI Express clock buffering
— CPU Reset and generation of CPU EREADY from downstream FPGAs
—JTAG buffering
— ABUS monitoring of power supplies and local temperature
— FPGA provides a PCIe endpoint, SPI control of the PS Interface FPGA, clock
dividers for the local power supplies, fan monitoring and ABUS mux and
ADC control
—Fan Power distribution
— Power Supplies: The input power supplies to the Infrastructure Board are
+12VD and +5V_STBY. The supplies generated by the Infrastructure Board
are: +3.3V_STBY, +5.1VD, +3.3VD, +2.5VD, and 1.0VD
A6 CPU Carrier
The A6 CPU Carrier provides power supply to A7 CPU and routes all the LAN,
GPIB, USB 2.0, PCIe, or Auxiliary I/O modules (Options CC1 or CC2 I/O
interface) connectors to the rear panel.
A7 CPU
The A7 CPU is a hybrid Type- 1/Type-10 COM (Computer- on-Module)
nanoETX Express assembly. It incorporates the Win CE Compact Framework
processor solution and is compatible with the PICMG® defined COM Express ™
standard and follows the Pin- out Type 1 along with providing common
instrument I/O interfaces. The A7 CPU controls all activities in the signal
generator. It translates information entered from the front panel keys, LAN,
GPIB, USB 2.0, PCIe or Auxiliary I/O modules (Options CC1 or CC2 I/O
interface) into machine level instructions and communicates these instructions
on the internal buses. The A7 CPU also monitors critical circuits for unleveled
and unlocked conditions, and reports these problems on the LCD Display.
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