138 Chapter 5
Digital IF Troubleshooting
A3 Digital I.F. Assembly Theory of Operation
A3 Digital I.F. Assembly Theory of Operation
NOTE Refer to Chapter 10 , “Block Diagrams”.
Data Acquisition
The 22.5 MHz IF comes from the A8 RF assembly. The input level to the A3
Digital IF assembly is −25 dBm. The IF input has a 25 MHz bandwidth
centered at 22.5 MHz. The analog circuitry leading to the ADC converts the
singled ended signal from the Analog IF to differential required by the ADC. In
addition, it is part of a filter, part of which is on the AIF, which improves
distortion. Finally, it couples in the dither signal. The ADC is a 14 bit device
sampling continuously at 90 Ms/Second.
Rear Panel Triggers
The board has two trigger inputs and two trigger outputs all used via a BNC
connector. The trigger inputs are used when an external device has a trigger
signal and the user wants to use that external trigger to trigger the signal
analyzer. The trigger outputs are used to synchronize other pieces of test
equipment to the CXA. These outputs are configurable through the
Input/Output menu via the front panel of the instrument.
The trigger inputs each allow trigger levels to be set from −5 to +5 volts using
the control DAC. The circuits have relatively high input impedance. The
trigger outputs have 50Ω source impedance with TTL drive levels into no load.
Control DAC
The control DAC is used to set trigger levels and the gain of the reconstruction
system. All three outputs can be adjusted from −2.5 to +2.5 volts.
Sample Rate Generator
The 10 MHz reference signal comes from the A16 Reference Assembly. This
signal is fairly high power at +10 dBm. The signal goes through a 10 MHz to
30 MHz tripler. A 0 to 5V 10 MHz square wave is generated. Capacitors form a
single-pole band pass filter to select the 3rd harmonic, 30 MHz.
The signal then passes through a 30 MHz to 90 MHz tripler. A 0 to 5V 30 MHz
square wave is generated. Capacitors form a single-pole band pass filter to
select the 3rd harmonic, 90 MHz.
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