Kontron CP3002 - Reset Status Register (RSTAT)

CP3002 Configuration
ID 1042-9252, Rev. 2.0 Page 4 - 9
P R E L I M I N A R Y
4.3.6 Reset Status Register (RSTAT)
The Reset Status Register is used to determine the host’s reset source.
Table 4-8: Reset Status Register (RSTAT)
REGISTER NAME RESET STATUS REGISTER (RSTAT)
ADDRESS 0x285
BIT NAME DESCRIPTION
RESET
VALUE
ACCESS
7 PORS Power-on reset status:
0 = System reset generated by software (warm reset)
1 = System reset generated by power-on (cold reset)
Writing a ’1’ to this bit clears the bit.
N/A R/W
6 - 3 Res. Reserved 0000 R
2 FPRS Front panel push button reset status (CP3002-HDD):
0 = System reset not generated by front panel reset
1 = System reset generated by front panel reset
Writing a ’1’ to this bit clears the bit.
0R/W
1 CPRS CompactPCI reset status (PRST signal):
0 = System reset not generated by CPCI reset input
1 = System reset generated by CPCI reset input
Writing a ’1’ to this bit clears the bit.
0R/W
0 WTRS Watchdog timer reset status:
0 = System reset not generated by Watchdog timer
1 = System reset generated by Watchdog timer
Writing a ’1’ to this bit clears the bit.
0R/W
Note ...
The Reset Status Register is set to the default values by power-on reset, not by
a warm reset.