Kyocera KM-4230 - Page 158

2A3/4
2-3-19
( 4 ) Reset circuit
+5 V DC
3
8
1
6
5
4
CK
RES
CT
VREF
50
7
CPU
IC7
Vcc
GND
RES
2
1
C7
2
VS
IC1
GROUND
GROUND
1
+
C17
R23
21
2
1
7
C2
2
2
1
C1
+5 V DC
1
R2
2
+5 V DC
R1
Figure 2-3-15 Reset circuit
V
CC
V
SH
V
SL
0.8 V DC
C
K
C
T
RES
T
CK
BA
Figure 2-3-16 CPU reset operation timing chart (abridged)
IC1 monitors the supply voltage and also determines if the CPU IC7 is operating
correctly. If the supply voltage VCC drops below VSL (approx. 4.2 V DC), the reset signal
(RES) is output to the CPU IC7 (A in the timing chart).
IC1 monitors the clock signal (CK) from pin 50 of the CPU IC7 which goes low
periodically. If the CPU IC7 fails, IC1 detects that the clock signal (CK) has stopped and
sends a reset signal (RES) to the CPU IC7 (B in the timing chart). To reset the CPU
IC7, pin 8 (RES) of IC1, which usually outputs 5 V DC, goes low and takes the level at
pin 7 of the CPU IC7 low.