Description of Self Test Items C-9
C.1.15 TRA AFE SPI Interface Test
Top test item
DSP FPGA and TRA FPGA communication self test (control interface)
Test content
Test whether the control interface communication between TRA FPGA and AFE’s SPI works well
via reading the register.
Analysis to test failure
The drive goes wrong if the test result appears Error.
SPI between TRA FPGA and AFE has communication error if the test result is FAIL.
Suggestion to failure test
Restart the device to perform the self test if the test result appears Error. It is necessary to restore
the device (OS+doppler) if Error re-appears.
It is recommended to change TRA board if the test result is FAIL.
C.1.16 TRA AFE Test Mode
Top test item
TRA AFE SPI test
Test content
Enter system test mode, write the data to TRA AFE, input delay RAM, re-read the data from
delay-channel memory to locate the channel and AFE clip.
Analysis to test failure
The drive goes wrong if the test result appears Error.
AFE clip goes wrong if the test result is FAIL.
Suggestion to failure test
Restart the device to perform the self test if the test result appears Error, which indicates the logic
error of DSP FPGA occurs. It is necessary to restore the device (OS+doppler) if Error re-appears.
It is recommended to change TRA board if the test result is FAIL.
C.1.17 TRA Transmission and Reception Function Test
Top test item
TRA AFE test mode
Test content
Test the coherence of 64 channels in transmitting and receiving: one channel transmits 2 V 1 M
PHV1 waveform each time, and analyzes whether the waveform is PHV1, and compares the
signal-to-noise ratio of this channel with others’.
Analysis to test failure
The drive goes wrong if the test result appears Error.
The waveform that the channel transmits is incorrect if the information “Open circuit of transmitting
and receiving channel: XXX” appears.
The transmission of this channel affects other channels if the information “Short circuit of
transmitting and receiving channel” appears.
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