APPX
Appendix 5 List of Special Register Areas
857
A
*1 When the value out of the range is specified, operation runs while its value is being regarded as max value of each range of multiple
CPU system configuration.
*2 There are restrictions on the firmware version of the supported CPU module and software version of the engineering tool. ( Page
1008 Added and Enhanced Functions)
SD792
and
SD793
PID limit setting (for
complete derivative)
0: Limit restriction
applied
1: No limit restriction
The limit restriction for each PID loop is specified as follows: (for
the PIDCONT instruction)
1 to 32: Loop 1 to 32
UALL
SD794
and
SD795
PID limit setting (for
incomplete derivative)
0: Limit restriction
applied
1: No limit restriction
The limit restriction for each PID loop is specified as follows: (for
the S.PIDCONT instruction)
1 to 32: Loop 1 to 32
UALL
SD796 Maximum number of
blocks used for the
multiple CPU
dedicated instruction
(for CPU No.1)
The maximum
number of blocks to
be used for the
dedicated instruction
Depending on the
number of CPU
modules which
constitute a multiple
CPU system, the
range is as follows.
*1
When constituting two
modules: 2 to 599
When constituting
three modules: 2 to
299
When constituting
four modules: 2 to
199
(Default: 2).
• The maximum number of blocks used for the multiple CPU
dedicated instruction is specified (for CPU No.1).
• When executing the multiple CPU dedicated instruction on CPU
No. 1, if the number of free blocks in the dedicated instruction
transfer area is less than the setting value on this register,
SM796 is turned on.
• This value is used as interlock signal for the continuous
executions of the multiple CPU dedicated instruction.
URn
*2
RnP
RnSF
SD797 Maximum number of
blocks setting used
for the multiple CPU
dedicated instruction
(for CPU No.2)
• The maximum number of blocks used for the multiple CPU
dedicated instruction is specified (for CPU No.2).
• When executing the multiple CPU dedicated instruction on CPU
No. 2, if the number of free blocks in the dedicated instruction
transfer area is less than the setting value on this register,
SM797 is turned on.
• This value is used as interlock signal for the continuous
executions of the multiple CPU dedicated instruction.
URn
*2
RnP
RnSF
SD798 Maximum number of
blocks setting used
for the multiple CPU
dedicated instruction
(for CPU No.3)
• The maximum number of blocks used for the multiple CPU
dedicated instruction is specified (for CPU No.3).
• When executing the multiple CPU dedicated instruction on CPU
No. 3, if the number of free blocks in the dedicated instruction
transfer area is less than the setting value on this register,
SM798 is turned on.
• This value is used as interlock signal for the continuous
executions of the multiple CPU dedicated instruction.
URn
*2
RnP
RnSF
SD799 Maximum number of
blocks setting used
for the multiple CPU
dedicated instruction
(for CPU No.4)
• The maximum number of blocks used for the multiple CPU
dedicated instruction is specified (for CPU No.4).
• When executing the multiple CPU dedicated instruction on CPU
No. 4, if the number of free blocks in the dedicated instruction
transfer area is less than the setting value on this register,
SM799 is turned on.
• This value is used as interlock signal for the continuous
executions of the multiple CPU dedicated instruction.
URn
*2
RnP
RnSF
SD816 Basic period Execution cycle An execution cycle (unit: second) of process control instructions is
set in real number.
URnP
RnPSF
SD817 RnP
RnPSF
SD818 Bumpless function
availability setting for
the S.PIDP instruction
0: Enabled
1: Disabled
The availability of the bumpless function for the S.PIDP instruction
is set.
URnP
RnPSF
SD820 Dummy device Dummy device A dummy device used in process control instructions is set. U RnP
RnPSF
SD821 RnP
RnPSF
No. Name Data stored Details Set by
(setting
timing)
CPU
SD792
b15 b1 b0
SD793
16
32
2
18
1
17
to
to
SD794
b15 b1 b0
SD795 17
12
18
16
32
to
to
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