Mitsubishi Electric MELSEC iQ-R-R00CPU - Page 863

APPX
Appendix 5 List of Special Register Areas
861
A
*1 The CPU module where this function can be used supports these special register areas.
SD954 Restoration function
of the CPU module
data backup/
restoration function
Restoration target
data setting
Set the target data to be restored with the CPU module data
restoration function.
0: All the target data
1: Device/label data only
2: All the target data except for the device/label data
URn
*1
SD955 Restoration function
setting
Set the CPU module data restoration function using the following
bit pattern. (Off: Disabled, On: Enabled)
b0: Automatic restoration setting
b1: Initialization setting at the automatic restoration
b13: Restoration setting for the latest data
b14: Restoration setting for the special relay and special register
b15: Setting for continuous operation with the status at backup
URn
*1
SD956 Restoration target
date folder setting
Store the target folder (date folder) of the CPU module data
restoration using BCD code.
(1) Day (1 to 31)
(2) Month (1 to 12)
(3) Year (last two digits) (0 to 99)
(4) Year (first two digits) (0 to 99)
[Example] To specify the date folder of June 15 2015, store
"H20150615".
URn
*1
SD957 URn
*1
SD958 Restoration target
number folder setting
Specify the target folder of the CPU module data restoration.
1 to 32767: Serial number of the backup folder (*****) in a date
folder (00001 to 32767)
URn
*1
SD959 Restoration error
cause
• The cause of an error that occurred during the CPU module data
restoration is stored.
0H: No error
Other than 0: For details on the values stored when an error
occurs, refer to the list of error codes. ( Page 703 List of error
codes)
• "0" is set at the start of the CPU module data backup.
S (Error) Rn
*1
SD960 Backup function of
the CPU module data
backup/restoration
function
Upper limit status for
the number of CPU
module backup data
This register indicates the set value of the upper limit for the
number of backup data in accordance with bit 5 of SD944.
Bit 5 of SD944 is off: 0
Bit 5 of SD944 is on: 1 to 100
S (Status
change)
Rn
*1
SD988 Memory copy
completion status
(latch)
Memory copy
completion status
(latch)
This register stores a value indicating the completion status of the
memory copy from the control system to the standby system.
• The value same as the SD1654 value is stored at the completion
or abend of the memory copy from the control system to the
standby system.
• Since data have been backed up in case of power failure, this
register holds the value indicating the latest memory copy
completion status from the control system to the standby system.
• This register is cleared to 0 by latch clear.
S (Status
change)
RnP
RnPSF
No. Name Data stored Details Set by
(setting
timing)
CPU
b1
b13b14b15
b0
0
SD957
b15 b8 b7 b0b31 b24 b23 b16
(1)(2)(3)(4)
SD956