19 TEST FUNCTION
19.1 External Input/Output Forced On/Off Function
237
19
Forced on/off timing
The following table lists the timing to reflect the registered data in the forced on/off registration settings to the input/output
devices or external outputs.
*1 For the precautions for using the direct access device, refer to the following.
Page 240 Precautions
*2 At input/output refresh execution where input/output refresh is registered for each program, and for interrupt programs.
*3 When an output device or external output is specified as a refresh device in multiple CPU refresh and the forced on/off function is
executed, the device is not forcibly turned on or off.
*4 Forced on/off is reflected only to output devices. (Since refresh to external outputs is not executed.)
*5 In redundant mode, forced on/off is reflected only to input devices on the standby system. (Since refresh from the CPU module to link
devices is not executed.)
*6 In redundant mode, whether external outputs to the standby system are reflected or not differs depending on the standby system output
setting. ( Page 236 Reflection to external outputs of the standby system)
*7 In redundant mode, refresh can be executed only for the module mounted on the extension base unit.
Inputs/outputs for which
forced on/off can be set
Reflection timing for the input devices Reflection timing for the output devices or
external outputs
*6
Input/output of the modules
mounted on the base unit
• END processing (at input refresh)
• At COM instruction execution (at input refresh)
• At instruction execution using the direct access input
(DX) (LD, LDI, AND, ANI, OR, ORI, LDP, LDF, ANDP,
ANDF, ORP, ORF, LDPI, LDFI, ANDPI, ANDFI, ORPI,
ORFI)
*1
• At execution of the RFS instruction and MTR instruction
• At execution of instructions used in the interrupt by the
system (UDCNT1, UDCNT2, SPD)
• At program execution
*2
• At execution of the inter-module synchronization cycle
program (I44)
• At execution of the multiple CPU synchronization
program (I45) and non-execution of the multiple CPU
synchronization program (I45) (at END processing)
*3
• At reflection of the tracking receive data to devices
• END processing (at output refresh)
• At COM instruction execution (at output refresh)
• At instruction execution using the direct access output (DY)
(OUT, SET, DELTA(P), RST, PLS, PLF, FF, MC, SFT(P))
*1
• At execution of the RFS instruction and MTR instruction
• At execution of instructions used in the interrupt by the
system (PLSY, PWM)
• At program execution
*2
• At execution of the inter-module synchronization cycle
program (I44)
• At reflection of the tracking receive data to devices
*4
Input/output of the CPU module
assigned to LX and LY of the
CC-Link IE Controller Network
module or MELSECNET/H
network module
*5
• END processing (at link refresh of the CC-Link IE Controller Network module or MELSECNET/H network module)
• At COM instruction execution (at link refresh of the CC-Link IE Controller Network module or MELSECNET/H network
module)
• At ZCOM instruction execution (at link refresh of the CC-Link IE Controller Network module or MELSECNET/H network
module)
Input/output of the CPU module
assigned to RX and RY of the
CC-Link module
*7
• END processing (at link refresh)
• At COM instruction execution (at link refresh)
• At ZCOM instruction execution (at link refresh)
Input/output of the CPU module
assigned to RX and RY of the
CC-Link IE Field Network
module
*5
• END processing (at link refresh)
• At COM instruction execution (at link refresh)
• At ZCOM instruction execution (at link refresh)
• At execution of the inter-module synchronization cycle program (I44)
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