690
APPX
Appendix 5 List of Special Register Areas
*1 When the value out of the range is specified, operation runs while its value is being regarded as max value of each range of multiple
CPU system configuration.
SD796 Maximum number of
blocks used for the
multiple CPU
dedicated instruction
(for CPU No.1)
The maximum number
of blocks to be used for
the dedicated
instruction
Depending on the
number of CPU
modules which
constitute a multiple
CPU system, the
range is as follows.
*1
When constituting two
modules: 2 to 599
When constituting
three modules: 2 to
299
When constituting four
modules: 2 to 199
(Default: 2).
• The maximum number of blocks used for the multiple CPU dedicated
instruction is specified (for CPU No.1).
• When executing the multiple CPU dedicated instruction on CPU No.1, if
the number of free blocks in the dedicated instruction transfer area is less
than the setting value on this register, SM796 is turned on.
• This value is used as interlock signal for the continuous executions of the
multiple CPU dedicated instruction.
U
SD797 Maximum number of
blocks setting used
for the multiple CPU
dedicated instruction
(for CPU No.2)
• The maximum number of blocks used for the multiple CPU dedicated
instruction is specified (for CPU No.2).
• When executing the multiple CPU dedicated instruction on CPU No.2, if
the number of free blocks in the dedicated instruction transfer area is less
than the setting value on this register, SM797 is turned on.
• This value is used as interlock signal for the continuous executions of the
multiple CPU dedicated instruction.
U
SD798 Maximum number of
blocks setting used
for the multiple CPU
dedicated instruction
(for CPU No.3)
• The maximum number of blocks used for the multiple CPU dedicated
instruction is specified (for CPU No.3).
• When executing the multiple CPU dedicated instruction on CPU No.3, if
the number of free blocks in the dedicated instruction transfer area is less
than the setting value on this register, SM798 is turned on.
• This value is used as interlock signal for the continuous executions of the
multiple CPU dedicated instruction.
U
SD799 Maximum number of
blocks setting used
for the multiple CPU
dedicated instruction
(for CPU No.4)
• The maximum number of blocks used for the multiple CPU dedicated
instruction is specified (for CPU No.4).
• When executing the multiple CPU dedicated instruction on CPU No.4, if
the number of free blocks in the dedicated instruction transfer area is less
than the setting value on this register, SM799 is turned on.
• This value is used as interlock signal for the continuous executions of the
multiple CPU dedicated instruction.
U
SD816 Basic period Execution cycle An execution cycle (unit: second) of process control instructions is set in
real number.
U
SD817
SD818 Bumpless function
availability setting for
the S.PIDP
instruction
0: Enabled
1: Disabled
The availability of the bumpless function for the S.PIDP instruction is set. U
SD819 Process value output
type setting for the
S.PHPL2 instruction
0: Decimal
1: Percent
Set the output type of the process value (PV) for the S.PHPL2 instruction of
process control instruction.
U
SD820 Dummy device Dummy device A dummy device used in process control instructions is set. U
SD821
No. Name Data stored Details Set by (setting
timing)
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