Mitsubishi Electric R64MTCPU - Page 88

86
2 MOTION DEDICATED PLC INSTRUCTION
2.3 Precautions
■Operation timing
Operation which executes each Motion dedicated instruction and turns on the Multiple CPU block information.
■Operation example
When multiple D(P).DDWR instructions (80 words) are executed simultaneously before turning on each complete device in
the 4 Multiple CPUs.
If the number of blocks used for each item is set as follows,
• Number of CPU dedicated instruction transmission area: 199 blocks (Initial value)
• Maximum number of blocks used for the Multiple CPU dedicated instruction setting (For CPU No.2) (SD797): 2 (Initial
value)
• D(P).DDWR number of blocks used: 6
And, when 33 D(P).DDWR instructions are issued within the Multiple CPU fixed cycle transmission cycle (0.888ms), the
number of blocks used is as follows.
6 (D(P).DDWR number of blocks)  33 (D(P).DDWR instructions) = 198 (Total blocks used)
Therefore, the number of empty blocks is as follows;
199 (Number of CPU dedicated instruction transmission area) - 198 (Total blocks used) = 1 (Number of empty blocks)
1 (Number of empty blocks) < 2 (Maximum number of blocks used for the Multiple CPU dedicated instruction setting (For CPU
No. 2) (SD797))
In the above case, the number of empty blocks is less than the "Maximum number of blocks used for the Multiple CPU
dedicated instruction setting (For CPU No. 2) (SD797)", therefore "Block information using Multiple CPU dedicated instruction
(For CPU No. 2) (SM797)" turns on.
If a new instruction is executed while in this status, it will be more than the permissible number of executions. However, this
can be avoided by using "Block information using Multiple CPU dedicated instruction (For CPU No. 2) (SM797)" as an
interlock.
ON
Sequence program
Motion dedicated
PLC instruction
CPU dedicated transmission
(Non-fixed cycle)
Dedicated instruction
transmission area usage
Block information using
Multiple CPU dedicated
instruction (For CPU No.2)
(SM797)
Instruction execution
END
Permissible number
of executions
Maximum number of blocks
used for the Multiple CPU
dedicated instruction setting
(For CPU No.2) (SD797)
Permissible number of executions or
more by the new instruction without an
interlock condition
Total dedicated
instruction transmission
area
Communication cycle
Transfer Transfer
Check at END
processing
Number of
empty blocks