167
Outline Adds two 32-bit data and stores the result in the specified area.
Program example
■ Operands
■ Explanation of example
• The contents of data registers DT1 and DT0 and the contents of data registers DT101 and DT100 are added when
trigger X0 turns ON. The added result is stored in data registers DT201 and DT200.
Bit position
DT101
0000
0000
11 8
0000
1000
30
Addend [S2+1, S2]: K558144
X0: ON
15
••12 •• ••
74
••
Bit position
DT201
0000
0000
11 8
0001
1100
30
Result [D+1, D]: K1871040
15 ••12 •• ••
74
••
Bit position
DT100
1000
0100
11 8
0100
0000
30
15 ••12 •• ••
74
••
Bit position
DT200
1000
1100
11 8
1100
0000
30
15 ••12 •• ••
74
••
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higher 16-bit area
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higher 16-bit area
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lower 16-bit area
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lower 16-bit area
Bit position
DT1
0000
0000
11 8
0001
0100
30
Augend [S1+1, S1]: K1312896
15 ••12 •• ••
74
••
Bit position
DT0
0000
1000
11 8
1000
0000
30
15 ••12 •• ••
74
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higher 16-bit area
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lower 16-bit area
+
Timer/Counter
EV
Relay
SVWRWYWX
Operand
S1
AAA A
A:
N/A: Not Available
Register
DT
A
IYIX
A N/A
HK
AA
Constant
Index
modifier
A
Index
register
Available
A
S2
A A A A A A N/A A A AA
N/A A A A A A N/A N/A N/A AA
D
F23
(D+)
32-bit data
[(S1+1, S1) + (S2+1, S2) → (D+1, D)]
Availability
Step
11 All series
6-3. Description of High-level Instructions
32-bit equivalent constant or lower 16-bit area of 32-bit data (for augend)
32-bit equivalent constant or lower 16-bit area of 32-bit data (for addend)
Lower 16-bit area of 32-bit data (for result)
Ladder Diagram
Boolean Non-ladder
Address Instruction
20
X0
F23 D
+ , DT0 , DT100 , DT200
S1
D
Trigger
S2
20
21
ST X 0
F 23 (D+ )
DT 0
DT 100
DT 200
S1
S2
D
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