Panasonic SL-VGU1-C

76
Chapter 3
Memory Map
Memory Assignment
In the I/O data sending / receiving area, the memory consists of the following data. Each table shows the data of
each address starting from the least signicant address (00H).
I/O data receiving area: Input data area + status data area
I/O data sending area: Output data area + status data area
● I/O data receiving area
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
00 7 6 5 4 3 2 1 0
01 15 14 13 12 11 10 9 8
02 23 22 21 20 19 18 17 16
······· ······· ······· ······· ······· ······· ······· ······· ·······
3E 503 502 501 500 499 498 497 496
3F 511 510 509 508 507 506 505 504
40 Error status Error 6 Error 5 Error 4 Error 3 Error 2 Error 1 Error 0
41 BUSY
Completion of
transmission
frame check
- - Number of I/O control points
● I/O data sending area
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
00 7 6 5 4 3 2 1 0
01 15 14 13 12 11 10 9 8
02 23 22 21 20 19 18 17 16
······· ······· ······· ······· ······· ······· ······· ······· ·······
3E 503 502 501 500 499 498 497 496
3F 511 510 509 508 507 506 505 504
40 Error cancel
- - - - - - -
41 -
Transmission
frame check
request
- - - - - -