2–26
Principles of Operation
LMI Hardware Summary
A Motorola 68EC030 microprocessor performs the DPU functions, a Zilog
Z8S180 (or Z80180) microprocessor handles the RTPU functions, and an
8032 microcontroller serves as the paper feed controller (PFC), which is part
of the RTPU. Actual implementation of this hardware blurs the distinctions
between the DPU and RTPU, since the 68EC030 has access to the parallel
port and the real–time functions of the dot plucker, which are RTPU
resources, while the Z8S180 has access to the nonvolatile memory
(NVRAM), which is a resource of the DPU. These possibilities exist because
of efficiencies in the hardware design; software maintains the functional
differences between the DPU and RTPU.
The LMI has seven data buses:
♦ Z8S180 local bus: an 8–bit data path
♦ Z8S180 local buffered I/O bus: an 8–bit data path
♦ 8032 local bus: an 8–bit data path
♦ Common or shared bus: 16–bit data path shared by the DPU and
Z8S180, arbitrated cycle by cycle
♦ Floppy controller bus: 8–bit data path from floppy disk to buffer memory
♦ DPU local bus
♦ Dot Plucker DRAM bus
The manner in which the LMI implements this hardware is depicted in
Figure 2–16 and Figure 2–17.
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