Quectel RG520N-AT - Page 24

5G Module Series
RG520N-AT_Hardware_Design 23 / 109
BT_CTS
62
DO
Clear to send
signal from the
module
Connect to the
peripheral’s CTS.
Debug UART
Pin Name
Pin No.
I/O
Description
DC
Characteristics
Comment
DBG_RXD
108
DI
Debug UART
receive
1.8 V
Test points must be
reserved.
DBG_TXD
105
DO
Debug UART
transmit
I2C Interface
Pin Name
Pin No.
I/O
Description
DC
Characteristics
Comment
I2C_SCL
77
OD
I2C serial clock
1.8 V
Pull each of them up
to VDD_EXT with an
external 4.7 kΩ
resistor. If unused,
keep them open.
I2C_SDA
78
OD
I2C serial data
I2S Interface*
Pin Name
Pin No.
I/O
Description
DC
Characteristics
Comment
I2S_WS
259
DIO
I2S word select
1.8 V
In master mode, it is
an output signal.
In slave mode, it is
an input signal.
I2S_SCK
256
DIO
I2S clock
In master mode, it is
an output signal.
In slave mode, it is
an input signal.
I2S_DIN
257
DI
I2S data in
I2S_DOUT
255
DO
I2S data out
MCLK
79
DO
Master clock
output for codec
If unused, keep it
open.
PCM Interface*
Pin Name
Pin No.
I/O
Description
DC
Characteristics
Comment
PCM_SYNC
71
DIO
PCM data frame
sync
1.8 V
Only used for
Bluetooth audio.