Quectel RG520N-AT - Page 25

5G Module Series
RG520N-AT_Hardware_Design 24 / 109
PCM_CLK
73
DIO
PCM clock
If unused, keep
them open.
PCM_DIN
74
DI
PCM data input
PCM_DOUT
76
DO
PCM data output
PCIe Interface
Pin Name
Pin No.
I/O
Description
DC
Characteristics
Comment
PCIE_REFCLK_P
40
AIO
PCIe reference
clock (+)
In root complex
mode, it is an output
signal.
In endpoint mode, it
is an input signal.
Requires differential
impedance of 85 Ω.
PCIE_REFCLK_M
38
AIO
PCIe reference
clock (-)
PCIE_TX0_M
44
AO
PCIe transmit 0 (-)
Requires differential
impedance of 85 Ω.
If unused, keep
them open.
PCIE_TX0_P
46
AO
PCIe transmit 0 (+)
PCIE_TX1_M
41
AO
PCIe transmit 1 (-)
PCIE_TX1_P
43
AO
PCIe transmit 1 (+)
PCIE_RX0_M
32
AI
PCIe receive 0 (-)
PCIE_RX0_P
34
AI
PCIe receive 0 (+)
PCIE_RX1_M
35
AI
PCIe receive 1 (-)
PCIE_RX1_P
37
AI
PCIe receive 1 (+)
PCIE_CLKREQ_N
36
OD
PCIe clock request
1.8 V
In root complex
mode, it is an input
signal.
In endpoint mode, it
is an output signal.
PCIE_RST_N
39
DIO
PCIe reset
In root complex
mode, it is an output
signal.
In endpoint mode, it
is an input signal.
PCIE_WAKE_N
30
OD
PCIe wake up
In root complex
mode, it is an input
signal.