Quectel RG520N-AT - Page 27

5G Module Series
RG520N-AT_Hardware_Design 26 / 109
BT_EN
64
DO
Bluetooth enable
control
WLAN_EN
222
DO
WLAN function
enable control
WL_SW_CTRL
180
DI
76.8 MHz system
clock request
WLAN_SLP_CLK
225
AO
32.768 kHz sleep
clock output
RF_CLK3_WL
246
AO
76.8 MHz system
clock output
Vmax = 1.08 V
Vnom = 1.05 V
Vmin = 1.02 V
SDX_TO_WL_
CTI
276
DO
-
1.8 V
Not used by default.
Keep it open.
WLAN_PA_
MUTING
162
DO
GPIO from SDX to
disable WLAN PA
WL_LAA_AS_EN
159
DO
GPIO allows SDR
to power on
monitoring for
WCN when WLAN
is sleeping or
disabled.
Additionally, the
control logic in
WLAN AON
domain allows
SDR to control 5G
WLAN xLNA (LNA
in FEMs).
WL_LAA_RX
201
DO
SoC signal to set
5G xLNA to high
gains or high
isolation when
both chains (LAA
and 5G WLAN)
are active
simultaneously. No
individual control
for each chain.
WL_TO_SDX_
CTI
275
DI
-
Not used by default.
Keep it open.
SDIO Interface
Pin Name
Pin No.
I/O
Description
DC
Comment