Quectel RG520N-AT - Page 28

5G Module Series
RG520N-AT_Hardware_Design 27 / 109
Characteristics
SDIO_VDD
60
PI
SDIO power
supply
1.8/2.95 V
configurable input.
If unused, connect it
to VDD_EXT.
SDIO_DATA0
49
DIO
SDIO data bit 0
The power
domain of SDIO
pins depends on
SDIO_VDD.
If unused, keep
them open.
SDIO_DATA1
50
DIO
SDIO data bit 1
SDIO_DATA2
51
DIO
SDIO data bit 2
SDIO_DATA3
52
DIO
SDIO data bit 3
SDIO_CMD
48
DIO
SDIO command
SDIO_CLK
47
DO
SDIO clock
SDIO_PWR_EN
53
DO
SDIO power
supply enable
1.8 V
SDIO_PWR_
VSET
56
DO
SDIO power
domain set
SDIO_DET
55
DI
SD card detect
Pull it up to
VDD_EXT with a
470 kΩ resistor.
If unused, keep it
open.
Antenna Interfaces
Pin Name
Pin No.
I/O
Description
Comment
ANT0
130
AIO
Antenna 0 interface:
- 5G NR: n77 TRX0
- LTE: LMB_TRX0 & HB_DRX
- Refarmed: LMB_TRX0 &
HB_TRX1
50 Ω impedance.
ANT1
157
AIO
Antenna 1 interface:
- 5G NR: n77 DRX MIMO
- LTE: LMB_PRX MIMO & HB_DRX
MIMO
- Refarmed: LMB_PRX MIMO &
HB_DRX MIMO
ANT2
166
AIO
Antenna 2 interface:
- 5G NR: n77 PRX MIMO
- LTE: LMB_DRX MIMO & HB_PRX
MIMO