Quectel RG520N-AT - Page 29

5G Module Series
RG520N-AT_Hardware_Design 28 / 109
- Refarmed: LMB_DRX MIMO &
HB_PRX MIMO
ANT3
184
AIO
Antenna 3 interface:
- 5G NR: n77 TRX1
- LTE: LMB_TRX1 & HB_TRX0
- Refarmed: LMB_TRX1 &
HB_TRX0
ANT_GNSS
193
AI
GNSS antenna interface:
- L1/L5
Antenna Tuner Control Interfaces*
Pin Name
Pin No.
I/O
Description
DC
Characteristics
Comment
SDR_GRFC0
171
DO
GRFC interfaces
dedicated for
external antenna
tuner control
1.8 V
If unused, keep
them open.
SDR_GRFC1
174
DO
SPI
Pin Name
Pin No.
I/O
Description
DC
Characteristics
Comment
SPI_CLK
210
DO
SPI clock
1.8 V
Only master mode is
supported.
SPI_CS
207
DO
SPI chip select
SPI_MISO
213
DI
SPI master-in
slave-out
SPI_MOSI
204
DO
SPI master-out
slave-in
ADC Interface
Pin Name
Pin No.
I/O
Description
DC
Characteristics
Comment
ADC0
241
AI
General-purpose
ADC interface
Voltage range:
0–1.875 V
Time Service and Repeater Interface
Pin Name
Pin No.
I/O
Description
DC
Characteristics
Comment
GPIO_32
98
DO
Supports time
service and
repeater functions;
supports 1PPS
pulse output and
frame
1.8 V
The pin can be
multiplexed into
AP2SDX_STATUS
function.
For details, contact
Quectel Technical