M
mantissa
see floating point number
memory access 9-6
via the BR register 9-22
via address in ACCU 1 9-8
memory card 3-10
memory organization 9-4
mode of operation of CPU 1-5
multiprocessor communication 6-62
application examples 10-53
assignment list 10-37
buffering data 10-17
data amount 10-15
initializing 10-33
modes 10-35
receive data 10-47
send data 10-40
sequence 10-15
test mode 10-14
multiprocessor mode
data exchange between CPUs
and CPs 10-7
data exchange with HDBs 10-8
programming 10-9
N
NAU (power failure) 4-19, 4-28
nesting depth 3-9
nesting program execution levels 4-6
no operation 3-33
O
O area see I/Os
operand areas 1-11
OR see results codes
organization block (OB)
general 2-12, 2-16
organization blocks
for communication in SOFT STOP 2-20
organization blocks (OB)
as user interfaces 2-18
for processing errors 2-20
special function organization blocks 6-4
OS (overflow latching)
see results codes
OV (overflow) see results codes
OVERALL RESET 4-14
P
P area
see I/Os
page area/DPR
occupied register 9-30
pages
accessing 9-29
parameters for DX 0 1-8
PARE (parity error) 5-28
PG functions 11-4
PG functions via S5 bus 11-27
PG interface module 11-17
PG screen form
for DX 0 parameter assignment 7-14
for generating DB1 10-10
PG software 1-18
PG submodule
installing 12-5
removing 12-6
PLC identification field 8-42
priority 1-6, 4-5, 4-7, 4-33, 4-42, 7-10
process image
outputs (PIQ) 1-5
defining/transferring 6-20
inputs (PII) 1-5
general 1-11
inputs (PII) 1-11
outputs (PIQ) 1-11
updating 4-29
PROCESS INTERRUPT 4-29
process interrupts
disable 3-72
enable 3-72, 4-45
process interrupts via input byte IB 0
general 4-41
user interfaces 4-41
programstoring 3-10
program blocks (PB) 2-12, 2-16
program execution level
general 4-6, 6-32
program execution levels 4-4
programming
general 1-15
programming language
C with S5-C compiler 1-18
GRAPH 5 1-18
SCL 1-18
STEP 5 1-18
programming language SCL 1-18
programming tools 1-18
List of Key Words
CPU 948 Programming Guide
C79000-G8576-C848-04
Index - 3