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Siemens CPU 948 User Manual
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8
Memory Assig
nment and
Mem
ory Org
aniz
ation
You
ca
n use
this ch
apte
r as a re
fe
re
nc
e sec
tion t
o ch
eck o
n
the
or
ganiz
ati
on of the
CPU 948 memo
ry. The cha
pter
also inc
ludes
imp
ortant inform
ation c
onta
i
ne
d in some of the syste
m data words.
CPU
948 Pro
grammi
ng Guid
e
C7
9000-G85
76-C84
8-04
8 - 3
326
328
Table of Contents
Default Chapter
3
Table of Contents
3
1 Introduction
9
Contents of Chapter 1
11
Introduction
11
Area of Application for the S5-155U with the CPU 948
12
Typical Mode of Operation of a CPU
13
Typical Mode of Operation of a CPU
14
The Programs in a CPU
15
Which Operands Are Available to the User Program
19
How Much Memory Is Available for the User Program
22
How to Tackle Programming
23
Programming Tools
26
Converting User Programs of the CPU 928B for the CPU 948
27
2 User Program
31
STEP 5 Programming Language
34
The LAD, CSF, STL Methods of Representation
34
Structured Programming
35
STEP 5 Operations
36
Number Representation
38
STEP 5 Blocks and Storing Them in Memory
42
Program, Organization and Sequence Blocks
46
Organization Blocks as User Interfaces
48
Organization Blocks for Special Functions
52
Function Blocks
53
Structure of Function Blocks
54
Programming Function Blocks
56
Calling Function Blocks and Assigning Parameters to Them
58
Special Function Blocks
63
Data Blocks
65
Creating Data Blocks
67
Opening Data Blocks
68
Special Data Blocks
71
3 Program Execution
73
Program Execution
75
Principle of Program Execution
76
Program Organization
77
Storing Program and Data Blocks
82
Processing the User Program
83
Definition of Terms Used in Program Execution
84
STEP 5 Operations with Examples
87
Basic Operations
91
Programming Examples in the STL, LAD and CSF Methods of Representation
106
Supplementary Operations
121
Executive Operations
131
Semaphore Operations
147
4 Operating Statuses and Program Execution Levels
153
Operating Statuses and Program Execution Levels
155
Program Execution Levels
156
STOP Mode
161
Soft Stop
161
Hard Stop
165
Overall Reset
166
START-UP Mode
168
MANUAL and AUTOMATIC COLD RESTART
169
MANUAL and AUTOMATIC WARM RESTART
170
Comparison between COLD RESTART and WARM RESTART
173
Retentive Cold Restart
174
Comparison of COLD RESTART and RETENTIVE COLD RESTART
175
User Interfaces for Start-Up
176
Extended AUTOMATIC WARM RESTART with the CPU 948 (HOT RESTART)
179
Interruptions During START-UP
180
RUN Mode
181
Cyclic Program Execution
182
Specifying Time and Interrupt-Driven Program Execution
184
Interrupt-Driven Program Execution
184
12 Appendix
195
5 Interrupt and Error Diagnostics
199
Interrupt and Error Diagnostics
201
Frequent Errors in the User Program
202
Error Information
203
Procedure for Error Analysis
206
Control Bits and Interrupt Stack
207
Control Bits
208
ISTACK Content
212
Example of Error Diagnosis Using the ISTACK
217
Error Handling Using Organization Blocks
218
Causes of Error and Reactions of the CPU
221
OB 19: Calling a Logic Block that Is Not Loaded (KB)
222
OB 19: Calling a Data Block that Is Not Loaded (KDB)
222
OB 23/24, ob 28/29:Timeout Error (QVZ)
223
OB 23/24, ob 28/29: Timeout Error (QVZ)
223
OB 25: Addressing Error (ADF)
224
OB 26: Cycle Time Exceeded Error (ZYK)
225
OB 27: (Substitution Error SUF)
226
OB 30: Parity Error and Timeout Error in the User Memory (PARE)
226
OB 32: Load and Transfer Error (TRAF)
227
OB 33: Collision of Timed Interrupts Error (WEFES/WEFEH)
228
OB 34: Error with G DB/GX DX (FEDBX)
230
OB 35: Communication Errors
230
OB 36: Error in Self-Test
231
Self-Test
232
Overview
232
Description of the Test Functions
233
Settings
235
Error Handling
236
6 Integrated Special Functions
239
Integrated Special Functions
241
Introduction
242
OB 121: Set/Read System Time
242
OB121: Set/Read System Time
246
OB 122: "Disable Interrupts" On/Off
250
OB 124: Delete STEP 5 Blocks
252
OB 125: Generate STEP 5 Blocks
255
OB 126: Define, Transfer Process Images
258
OB 129: Battery State
263
OB 131: Delete Accus 1, 2, 3 and 4
264
OB 132/133: Roll-Up Accu/Roll-Down ACCU
265
6.10 ob 141: "Disable Single Cyclic Timed Interrupts" On/Off
267
6.11 ob 142: "Delay All Interrupts" On/Off
270
6.12 ob 143: "Delay Single Cyclic Timed Interrupts" On/Off
273
6.13 ob 150: Set/Read System Time
276
6.14 ob 151: Set/Read Time for Clock-Controlled Interrupt
281
6.15 ob 153: Set/Read Time for Delayed Interrupt
288
6.16 ob 180: Variable Data Block Access
291
OB 181: Test Data Blocks (DB/DX)
295
6.18 ob 182: Copy Data Area
297
OB 202 to 205: Multiprocessor Communication
300
OB 222: Restart Cycle Monitoring Time
301
OB 223: Compare Start-Up Modes
302
OB 254/255: Copy/Duplicate Data Blocks
303
Extended Data Block DX 0
307
7 Extended Data Block DX 0
309
Application
310
Structure of DX 0
311
Example of Input in DX 0
313
Parameters for DX 0
314
Examples of Parameter Assignment
318
Parameter Assignment Using the PG Screen Form
320
8 Memory Assignment and Memory Organization
325
Memory Assignment and Memory Organization
327
Structure of the Memory Area
328
Memory Assignment in the CPU 948
329
Memory Assignment for the System RAM
330
Memory Assignment for the Peripherals
332
User Memory Organization in the CPU 948
334
Block Headers in User Memory
336
Block Address List in Data Block DB 0
337
RI/RJ Area
338
RS/RT Area
339
Bit Assignment of the System Data Words
342
Addressable System Data Area
366
9 Memory Access Using Absolute Addresses
371
Memory Access Using Absolute Addresses
373
Introduction
374
Memory Access Via Address in ACCU 1
378
LIR/TIR: Loading to or Transferring from a 16-Bit Memory Area Indirectly
379
Examples of Access to DW > 255
385
LDI/TDI: Loading to or Transferring from a 32-Bit Memory Area Indirectly
387
Transferring Memory Blocks
389
Operations with the Base Address Register (BR Register)
392
Operations for Transfer between Registers
393
Accessing the Local Memory
394
Accessing the Global Memory
395
Accessing the Dual-Port RAM Memory
399
Multiprocessor Mode and Com Munication in the S5-155U
405
Multiprocessor Mode and Communication in the S5-155U
407
10 Multiprocessor Mode
408
Exchanging Data Via IPC Flags
409
Exchanging Data Via Handling Blocks
412
What Needs to be Programmed for the Multiprocessor Mode?
413
Starting up in the Multiprocessor Mode
417
Test Mode
418
Multiprocessor Communication
419
How the Transmitter and Receiver Are Identified
420
Why Data Is Buffered
421
How the Buffer Is Processed and Managed
422
System Start-Up
425
Calling Communication Obs
426
How to Assign Parameters to Communication Obs
427
How to Evaluate the Output Parameters
428
Runtimes of the Communication Obs
435
INITIALIZE Function (ob 200)
437
Call Parameters
439
Output Parameters
442
SEND Function (ob 202)
444
Function
444
Call Parameters
444
Input Parameters
444
Output Parameters
446
SEND TEST Function (ob 203)
449
Function
449
Call Parameters
449
Input Parameters
449
Output Parameters
449
RECEIVE Function (ob 204)
451
Call Parameters
451
Input Parameters
451
Output Parameters
452
RECEIVE TEST Function (ob 205)
455
Function
455
Call Parameters
455
Input Parameters
455
Output Parameters
455
10.9 Applications
457
Calling the Special Function ob Using Function Blocks
457
Transferring Data Blocks
464
Extending the IPC Flag Area
470
11 PG Interfaces and Functions
485
PG Interfaces and Functions
487
Overview
488
PG Functions
489
Info
490
Installation
491
Program Test
492
Serial Link PG - PLC Via 1St or 2Nd Serial Interface
500
Parallel Operation of Two Serial PG Interfaces
501
Installation
503
Sequence in Certain Operating Situations
505
PG Functions Via the S5 Bus
511
How the PG Functions Work Via the S5 Bus
513
Installation and Getting Started
515
Condition Codes Indicating Problems
519
13 Indexes
537
5
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Siemens CPU 948 Specifications
General
Brand
Siemens
Model
CPU 948
Category
Controller
Language
English
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