5.4.1
Control Bits When you display the ISTACK on your programmer, the status of the
control bits is indicated on the first page (see Fig. 5-1).
Note
The ISTACK screen form shown in Fig. 5-1 reflects the PG
software STEP 5/ST, Version 6.3 or STEP 5/MT Version 6.0 with
the "Delta diskette CPU 948". In older versions of the PG
software, the abbreviations of the control bits may be different.
The meaning of the control bits, however, is as described in the
following tables.
You can output the control bits in every mode. They mark the current or
previous status of the CPU and provide information on specific features
of the CPU and your STEP 5 program.
The control bits listed under ERROR IDS mark errors that can occur
in the RESTART (e.g., during an initial cold restart) and RUN (e.g.,
during time-controlled program processing) modes. If several errors
occur, all errors are displayed in the control bits.
CONTROL BITS
SYSTEM DESCRIPTION:
E0VH
GEP
BATT
EINP
MEHRP
SYNCR
TEST
STOP CAUSE:
START-UP IDs:
ERROR IDs:
PGSTP
UPROG
X
NEUDF
X
X
AWEG
QVZIN
FE2S
FDX0
X
BSTG BEFG
MCG
X
HALT
STP
STS
STOPS
BEARBE
USYS UANL
AFEL
SYSFHL
WIEDF
URLDF NEUZU
WIEZU URLER
ANEG
MSEG
PARIN
BSTKF
BSTEF
UMCG
MODUN
SRAMF
UAFEHL
KDB1
KDX0
FDB1
FMODE
FEDBX QVZNIO WEFES
DB0UN
Fig. 5-1 Example of the first screen form page "OUTPUT ISTACK": control bits
Control Bits and Interrupt Stack
CPU 948 Programming Guide
5 - 10 C79000-G8576-C848-04
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