3.5.5
Semaphore Operations If two or more CPUs in one programmable controller (see Chapter 10)
require access to the same global memory area (peripherals, CPs, IPs),
there is a danger that one CPU will overwrite the data of another CPU
or that one CPU could read invalid intermediate data statuses of
another CPU and misinterpret them. You must therefore coordinate
CPU accesses to the common memory areas.
You can coordinate the individual CPUs using the SED and SEE
operations.
You can, for example, program the following coordination between two
CPUs: a CPU involved in multiprocessing can only access the common
memory area after it has successfully set a declared semaphore (SES). A
semaphore xx can only be set by a single CPU. If a CPU fails to set (i.e.
disable) the semaphore, it cannot access the memory area. In the same
way, a CPU can no longer access the memory once it has released the
semaphore again (SEE).
SED/SEE disable/enable
semaphore
(non-system operations)
Operation Operand Function
SED
SEE
0 to 31
0 to 31
Disable (set) a semaphore
Enable (release) a semaphore
evaluation of the result of the operation via
CC 0/CC 1
Note
The SED xx and SEE xx operations must be programmed in all
CPUs that require synchronized access to a common global
memory area.
Standard FBs, handling blocks and blocks for multiprocessor
communication manage the coordination internally. If you use
these blocks, you do not need to program the operations SEE xx
and SED xx.
Table 3-29 Disable/enable semaphore
Semaphore Operations
CPU 948 Programming Guide
C79000-G8576-C848-04
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