9.2.1
LIR/TIR: Loading to or
Transferring from a 16-Bit
Memory Area Indirectly
The following table shows which register numbers you can use with
the CPU 948 for the LIR and TIR operations and how these are
assigned.
Register no. Register assignment (each 16 bits wide)
0 ACCU-1-H (left word of ACCU1, bits 16 to 31)
1)
1 ACCU-1-L (right word of ACCU1, bits 0 to 15)
1)
2 ACCU-2-H
3 ACCU-2-L
5 Block stack pointer (offset)
6 DBA (data block start address register)
8 DBL (data block length register)
9 ACCU-3-H
10 ACCU-3-L
11 ACCU-4-H
12 ACCU-4-L
1)
Loading the contents of an addressed memory register into register ’0’or ’1
overwrites the address stored in ACCU 1.
Registers 4, 7, 13, 14 and 15 do not exist on the CPU 948. LIR/TIR
operations with these register numbers must not be used.
LIR/TIR: with 8-bit
memory areas
If you use the LIR and TIR operations to access memory areas that are
only 8 bits wide, remember that
•• the LIR operation overwrites the high byte of the registers with
non-defined values (except for flags, PIQ, PII; with these areas,
FFH is written in the high byte)
and
•• the TIR operation transfers only the low byte of the register. The
high byte of the register is lost.
Figs. 9-3 and 9-4 illustrate the difference when accessing word and
byte-oriented memory areas using LIR/TIR.
Table 9-2 16-bit register for LIR/TIR
Memory Access via Address in ACCU 1
CPU 948 Programming Guide
C79000-G8576-C848-04
9 - 9
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