Siemens CPU 948 - Page 380

19 0
15
0
19 0
ACCU 1
ACCU 1
Register n
Register n
addressed
memory
location
addressed
memory
location
15
0
LIR n
TIR n
15 0
Fig. 9-3 LIR/TIR with 16-bit memory areas (word-oriented)
19 0
15
0
19 0
ACCU 1
ACCU 1
Register n
Register n
addressed
memory
location
addressed
memory
location
15
0
LIR n
xx
xx
TIR n
7
0
Fig. 9-4 LIR/TIR with 8-bit memory areas (byte-oriented)
Memory Access via Address in ACCU 1
CPU 948 Programming Guide
9 - 10 C79000-G8576-C848-04