Registers 0 to 3 and 9 to 12:
ACCUs 1, 2, 3 and 4
During program processing, the accumulators are used as buffers for
the CPU. The TIR operation transfers the contents of the accumulators
into absolutely addressed memory registers. The LIR operation loads
the contents of absolutely addressed memory registers into the
accumulators. The absolute address of the memory locations is in
ACCU 1, bit number 0 to 19.
Examples
Register 6: DBA (Data Block
Start Address)
When you open a data block or an extended data block using the
C DB or CX DX operations, the address of DW 0 in the opened data
block is loaded into register 6. The block address list in DB 0 contains
this address.
The DBA register is set to ’0’ before each OB 1 call.
The DBA register remains the same if one of the following occurs:
•• a jump operation (JU/JC) causes program processing to continue in
a different block,
or
•• the CPU activates a different program processing level.
The contents of the memory location with address E F800 are loaded in flag
word FW 100.
:L DH 000E F800 Load address E F800 of the memory location in ACCU 1
:LIR 1 Load the contents of the memory location addressed by
: ACCU 1 in register 1 (= ACCU-1-L)
:T FW 100 Store the contents of address E F800 in flag word FW 100
:BE
The content of the flag word 200 is transferred to the memory location with
address E F800.
:L FW 200 Load flag word FW 200 in ACCU 1
:L DH 000E F800 Load address E F800 to which the data will be trans-
: ferred in ACCU 1 (flag word FW 200 to ACCU 2)
:TIR 3 Transfer the contents of register 3 = ACCU-2-L in to
: the memory location addressed by ACCU 1
:BE
Memory Access via Address in ACCU 1
CPU 948 Programming Guide
C79000-G8576-C848-04
9 - 11
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