The following tables explain the meaning of the individual bits.
SYSTEM DESCRIPTION
Bit Meaning
E0VH Input byte IB 0 (process interrupts) exists, i.e. the digital
input module addressed with ’0’ was plugged in during
the last cold restart and the module acknowledged.
GEP Programmable controller has a central back-up battery.
BATT Battery failure in the central controller (BAU)
EINP Single processor operation
MEHRP Multiprocessing operation
SYNCR Start-up of the CPUs in multiprocessing operation is
synchronized
TEST Test operation
BSTG DX-0 setting "interrupts at block boundaries"
BEFG DX-0 setting "interrupts at operation boundaries
MCG Memory card inserted
STOP CAUSE (see RS 7)
Bit Meaning
PGSTP STOP mode set from programmer
HALT Multiprocessor STOP mode:
a) Selector switch on the coordinator (COR) is
in the STOP position
or
b) Stop status caused by command STOP operation
from system program when the corresponding
error OB is not loaded and an error occurs
STS STOP mode caused by STEP 5 operation ’STS’ (after
executing an operation)
STOPS STOP mode caused by setting the mode selector to the
STOP position
BEARBE STOP mode after the PROGRAM TEST END
programmer function
Table 5-1 Meaning of the control bits SYSTEM DESCRIPTION
Table 5-2 Meaning of the control bits STOP CAUSE
Control Bits and Interrupt Stack
CPU 948 Programming Guide
C79000-G8576-C848-04
5 - 11
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