Technology instructions
9.1 High-speed counter
S7-1200 Programmable controller
412 System Manual, 03/2014, A5E02486680-AG
Since the interrupts occur at a much lower rate than the counting rate of the HSC, precise
control of high-speed operations can be implemented with relatively minor impact to the scan
cycle of the CPU. The method of interrupt attachment allows each load of a new preset to be
performed in a separate interrupt routine for easy state control. Alternatively, all interrupt
events can be processed in a single interrupt routine.
HSC input channel selection
Use the following table and ensure that the CPU and SB input channels that you connect
can support the maximum pulse rates in your process signals.
Note
CPU and SB input channels (V4 or later firmware) have configurable input filter times
Earlier firmware versions had fixed HSC input channels and fixed filter times that could not
be changed.
er versions allow you to assign input channels and filter times. The default input filter
setting of 6.4 ms may be too slow for your process signals. The filter times for the HSC
inputs must be optimized for your HSC application.
See "Configuring digital input filter times
144)" for details.
Table 9- 4 CPU input: maximum frequency
A/B Quadrature phase
mode
1212C
1214C and 1215C
1217C
Ib.2 to Ib.5
(.2+, .2- to .5+, .5-)
1 MHz 1 MHz
Table 9- 5 SB signal board input: maximum frequency (optional board)
A/B Quadrature phase
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