STEP 5 Operations S5-115F Manual
RS flip-flop for a latching signal output
”1” at input I 2.7 sets flip-flop Q 3.5 (signal state ”1”). If
the signal state at input I 2.7 changes to ”0”, the state of
output Q 3.5 is maintained, i.e., the signal is latched.
A ”1” at input I 1.4 resets the flip-flop (signal state ”0”).
When the ”SET” signal (input I 2.7) and the ”RESET” signal
(input I 1.4) are applied at the same time, the scanning
operation that was programmed last (in this case A I 1.4) is
in effect during processing of the rest of the program. In
this example, resetting output Q 3.5 has priority.
Circuit Example
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I 1.4
Q 3.5
I 2.7
I 2.7
Q 3.5
STL
S
R Q
LADCSF
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I 1.4
I 2.7
I 1.4
Q 3.5
S
R
Q
A I 2.7
S Q 3.5
A I 1.4
R Q 3.5
NOP 0
*
* NOP 0 is necessary if the program is to be represented in LAD or CSF form on the PG 635, PG 670, PG 675, PG 685, PG 695
or PG 750 programmers. During programming in LAD and CSF, such ”NOP 0” operations are allotted automatically.
3-8
EWA 4NEB 811 6149-02
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