STEP 5 Operations S5-115F Manual
3.5 Sample Programs
Sections 3.5.1 through 3.5.3 provide a few sample programs that you can enter and test in all three
methods of representation on a programmer with a screen (e.g. the PG 675).
3.5.1 Transitional-Pulse Relay (Edge Evaluation)
F 12.0
F 4.0
Circuit DiagramExample
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I 1.7
On each leading edge of the signal at input I 1.7, the AND
condition ”A I 1.7 and AN F 4.0” is satisfied; the RLO is ”1”.
This sets flags F 4.0 and F 12.0 (”edge flags”).
In the next processing cycle, the AND condition ”A I 1.7 and
AN F 4.0” is not satisfied since flag F 4.0 has already been set.
Flag F 12.0 is reset.
Therefore, flag F 12.0 is ”1” for only one program run.
When input I 1.7 is switched off, flag F 4.0 is reset.
This resetting prepares the way for evaluation of the next
leading edge of the signal at input I 1.7.
F 12.0
I 1.7
F 12.0 F 4.0 F 4.0
(#)
S
R
Q
I 1.7
I 1.7
LADSTL CSF
A I 1.7
AN F 4.0
= F 12.0
A F 12.0
S F 4.0
AN I 1.7
R F 4.0
NOP 0
F 12.0
I 1.7 &
(#)
I 1.7
F 4.0
F 4.0
S
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3-72
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