S5-115F Manual STEP 5 Operations
Conditon code generation for shift operations
Execution of shift operations sets CC 0 and CC 1. It does not affect the overflow condition code
( Table 3-33).
Code setting depends on the state of the last bit shifted out.
Table 3-33. Condition Code Settings for Shift Operations
Possible
jump operations
OVCC 0CC 1
Condition codes
Value of
the last bit
shifted out
”0” 0 0 JZ
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”1” 1 0 JN, JP
Condition code generation for conversion operations
The formation of the two's complement (CSW) sets all condition codes ( Table 3-34). The state of
the condition codes is based on the result of the conversion function.
Table 3-34. Condition Code Settings for Conversion Operations
Possible
jump operations
OVCC 0CC 1
Condition codes
Result after
arithmetic operation
is executed
- 32768* 0 1 1 JN, JP, JO
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- 32767 to - 1
0
+1 to +32767
0
0
1
1
0
0
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JN, JM
JZ
JN, JP
* This number is the result of the conversion of KH = 8000.
EWA 4NEB 811 6149-02
3-71
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