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3: System Overview
memory block, it is in an exclusive state. And when more than one processor has a copy of the
block, it is in a shared state; a bit vector indicates which caches may contain a copy.
When a processor modifies a block of data, the processors that have the same block of data in their
caches must be notified of the modification. The SGI UV 2000 server series uses an invalidation
method to maintain cache coherence. The invalidation method purges all unmodified copies of the
block of data, and the processor that wants to modify the block receives exclusive ownership of
the block.
Non-uniform Memory Access (NUMA)
In DSM systems, memory is physically located at various distances from the processors. As a
result, memory access times (latencies) are different or “non-uniform.” For example, it takes less
time for a processor blade to reference its locally installed memory than to reference remote
memory.
Reliability, Availability, and Serviceability (RAS)
The SGI UV 2000 server series components have the following features to increase the reliability,
availability, and serviceability (RAS) of the systems.
• Power and cooling:
– IRU power supplies are redundant and can be hot-swapped under most circumstances.
Note that this might not be possible in a “fully loaded” system. If all the blade positions
are filled, be sure to consult with a service technician before removing a power supply
while the system is running.
– IRUs have overcurrent protection at the blade and power supply level.
– Fans are redundant and can be hot-swapped.
– Fans run at multiple speeds in the IRUs. Speed increases automatically when
temperature increases or when a single fan fails.
• System monitoring:
– System controllers monitor the internal power and temperature of the IRUs, and can
automatically shut down an enclosure to prevent overheating.
– All main memory has Intel Single Device Data Correction, to detect and correct 8
contiguous bits failing in a memory device. Additionally, the main memory can detect
and correct any two-bit errors coming from two memory devices (8 bits or more apart).
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