Sony MVC-FD91 - Camera;FDD Interface Block Diagram

MVC-FD91
3-2. CAMERA/FDD INTERFACE BLOCK DIAGRAM
3-5 3-6 3-7 3-8
IC401 !∞,!§
5Vp-p
60nsec
IC401 !¢
3Vp-p
60nsec
IC401 8
1.8Vp-p
78µsec
IC401 2,4
7.5Vp-p
78µsec
IC401 1,3
8Vp-p
78µsec
IC101 2 – !¡
CAMERA REC/PB
3.1Vp-p
60nsec
IC103 #§,$∞
CAMERA REC/PB
3.8Vp-p
60nsec
IC101 !§
CAMERA REC/PB
60nsec
4.0Vp-p
IC101 @§ CAMERA REC
1.4Vp-p
78µsec
IC102 $º,$¡
CAMERA REC
8Vp-p
78µsec
IC102 $™,$¢
CAMERA REC
7.5Vp-p
78µsec
IC102 4
CAMERA REC/PB
3.8Vp-p
30nsec
IC102 @∞
CAMERA REC/PB
4.0Vp-p
60nsec
IC102 9
CAMERA REC
4Vp-p
60nsec
IC102 !™,!£
CAMERA REC
3Vp-p
60nsec
IC601 5
3.8Vp-p
60nsec
IC601 #¶
3.8Vp-p
60nsec
IC601 $§
3.3Vp-p
20msec
IC601 !ª
0.16Vp-p
78µsec
IC601 @£
0.18Vp-p
78nsec
IC601 $¶
3.3Vp-p
78µsec
IC601 !¢
0.1Vp-p
78µsec
IC851 *º
7.41MHz
2.0Vp-p
IC801 *£
5.0Vp-p
16.26MHz
IC601 $™
CAMERA REC/PB
3.2Vp-p
4.0MHz