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5 - Peripherals
05-wgd2
Bit 6 must be set high at all times. Setting it low immediately resets the microcontroller. This
may be used to reset the whole application if needed under program control (e.g. a message
received is coded as a reset request).
Bits 5 through 0 select the time-out value in increments of 12 288 machine cycles, which is
roughly 1.5 ms at full speed. The time-out may be set in up to 64 increments, that is about 98
ms at full speed.
The watchdog control register is a read-write register, thus it is possible to read the time re-
maining in the watchdog counter. If the watchdog is not activated (by setting bit 7 to one for the
software-activated version), it can be used as a real-time clock by simply reading its value.
To rewind the watchdog, it is sufficient to write a new value to it, keeping the two high-order
bits high. It is possible to rewind the watchdog to different value, depending on the circum-
stances, to allow a shorter or longer time-out.
In the 72311, the watchdog has an extra register, the Watchdog Status Register (WDGSR)
that only has one meaningful bit, WDOGF.
WGDA T6
T4
T5
T3 T2 T1
T0
Reset
100 0000
011 1111
Downcount
transition producing
a watchdog reset
up to 64 decrements
Watchdog control register
Clock divider
1/12288
f
cpu
ST72311 Watchdog timer operating description
72311: software- or hardware-
activatedwatchdogselectedinthe
Option byte in the Epromer or
as a mask option
WDOGF
Watchdog status register
Flag bit set by a watchdog reset
cleared by software or power-on reset
Software-activated:
Activation bit is
cleared by hardware
after a reset,
canbesetonce
by software.
Can only be cleared
by another reset
Hardware-activated:
WGDA = 1 permanently
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