ST ST7 - Output Compare Operation

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5 - Peripherals
05-Capt
5.5.4 Output compare operation
The output compare is a feature that produces an event when the current value of the free-
running counter matches the value of a register called Output Compare Register (OCnR,
where n is 1 or 2 for the first of the second compare registers, respectively).
This event may produce various effects:
 An interrupt request;
Input capture and corresponding interrupt mechanism:
dia
g
ram for channel 1, timer A
ICF1*
Timer A status
register (TASR)
I
Condition code
register (CCR)
ICIE
Timer A control
register 1 (TACR1)
Input capture
interrupt to
the core
1
0
Input
capture 1
pin
IEDG1
Free running counter
16 bit input capture register
TAIC1HR, TAIC1LR
(Read only registers)
load
ICF1 : Input capture flag 1 bit (bit 7 of TASR)
ICIE : Input capture interrupt enable bit (bit 7 of TACR1)
(common bit to both channels of the timer)
IEDG1 : Input edge 1 bit (bit 1 of TACR1)
I : Global interrupt enable bit (bit 3 of CCR)
*ICF1 is cleared by reading
the TASR followed by an access
to TAIC1LR