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5-Peripherals
RWU, when set, places the receiver in a mode where the RDRF bit is not set and a receive
interrupt is not generated, even when characters are received. The SCI exits this sleep state
only when one of the following events occur: the ninth bit is a one, with the word length set
to 9; or when an idle line condition is detected. Which of these events wakes up the SCI
depends on the state of the WAKE bit in Control Register 1. If cleared, the Idle line condition
wakes the SCI; if set, the ninth bit set does it.
SBRK sets the transmit line to the Break condition. The line remains in this condition until
SBRK is cleared. No characters can be sent while in Break condition.
5.8.5 Using the Wake-Up feature in a multiprocessor system
Waking-uptheSCIwhentheninthbitissetallowsyoutobuildanetworkofmicrocontrollers,
all connected to the same line. Then, by convention, if a device sends a character with that bit
set, it can be considered by all microcontrollers as an address character. Ifthe value of the ad-
dress received does not match the local address, a microcontroller has nothing to do, since it
will only be interrupted when addresses are received. If the address matches the local ad-
dress, the microcontroller may clear its RWU bit, thus switching the SCI to normal mode. It
then receives all the characters. Next time an address is received, and if that address is not its
own, the microcontroller just sets its RWU bit and from that time on, it is not disturbed by the
traffic on the line.
5.8.6 Handling the interrupts
All the interrupt causes of the SCI share the same interrupt vector. Thus, the same interrupt
service routine is used forall causes, and the interrupt service routine must start by testing the
Status Register bits to know which event caused the interrupt.
For this reason, and as ususal for most of the ST7 peripherals, once an interrupt has been ac-
cepted and the interrupt service routine is started, the interrupt request must be cleared by
program. The way to do it depends on the interrupt considered.
The receive interrupt request bit is cleared by a read of the Status Register followed by a
read of the Data Register. Since these actions must anyway be done in the program, first
testing which bit is set in the Status Register and then reading the received character, the
clearing of the interrupt request is transparent to the programmer.
The transmit interrupt request bit (either TD or TDRE) is cleared when the Status Register
is read and the Data Register is written. As above, this is transparent to the programmer.
The IDLE condition interrupt request bit is only reset by resetting the RE (Receive Enable)
bit, even temporarily.
The error bits OR, NF and FE are also only reset by resetting RE.
Using interrupt-driven software to handle the SCI is generally a good solution. A received
character or string is written to a buffer, then the main program is informed that something has
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