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5 - Peripherals
05-EI251
5.3.2 ST72311 I/O Ports
Bits 0 to 3 of Port A and bits 0 to 2 of Port F of are configurable as interrupt inputs. The option
for the edge and level of these inputs is set by bits PEI0 and PEI1 (external interrupt polarity
option) in the miscellaneous register. The interrupt vector for Port A is FFF6-FFF7, and FFF4-
FFF5 for Port F.
All bits of Port B are configured by the PEI2 and PEI3 bits in the same register. However, bits
0 to 3 are assigned to the vector at FFF2-FFF3, while bits 4 to 7 are assigned to the vector at
FFF0-FFF1.
Note: PB5 to PB7 are not available on the smaller packages (J series).
PEI3
PEI2
PEI1 PEI0MC0
--
SMS
ST72251
00
10
01
11
Falling edge and low level (reset state)
Falling edge only
Rising edge only
Rising and falling edge
External interrupt polarity Options EI0 and EI1
of the Miscellaneous register
EI1: Ports B & C
vector address:
FFF8-FFF 9
EI0: Port A
vector address:
FFFA-FFFB
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