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5-Peripherals
5.1.2 ST72311 Miscellaneous Register
The SMS bit works the same way as in the ST72251 (see previous paragraph), but in addition,
the two bits PSM1 and PSM0 (prescaler for slow mode) select the supplementary division rate
between 2 and 16.
The bit MCO (main clock out), when set, enables a clock signal with this frequency to be
output on bit 0 of port F (PF0).
05-misc2
PEI3 PEI2 PEI1
PEI0
MC0
PSM1
SMS
Main Clock Out, Slow Mode Select and Prescaler bits
of the ST72311 Miscellaneous Register
%2
Oscillator
PF0
normal
I/O port
f
CPU
to the core and
peripherals
0 normal mode
1 slow mode
0 normal I/O
1Pf0=f
CPU
ST72311
PSM2
%2 0 0
%8 0 1
%4 1 0
%16 1 1
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