ST ST7 - Page 5

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Table of Contents
4ARCHITECTUREOFTHEST7CORE.......................................62
4.1 POSITIONOFTHEST7WITHINTHESTMCUFAMILY....................62
4.2 ST7CORE........................................................63
4.2.1 Addressingspace ......................................................65
4.2.2 Internalregisters.......................................................65
4.2.2.1 Accumulator(A)...................................................65
4.2.2.2 Condition Code register (CC) ........................................65
4.2.2.3 Index registers (X and Y) ............................................67
4.2.2.4 Program Counter (PC) . .............................................68
4.2.2.5 StackPointer(SP) .................................................68
4.3 INSTRUCTION SET AND ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . 70
4.3.1 A word about mnemonic language .........................................70
4.3.2 Addressingmodes .....................................................72
4.3.3 Instructionset .........................................................73
4.3.4 Coding of the instructions and the address ..................................74
4.3.4.1 Prefixbyte .......................................................74
4.3.4.2 Opcodebyte .....................................................75
4.3.4.3 The addressing modes in detail . . . ....................................77
4.4 ADVANTAGES OF THE ST7 INSTRUCTION SET AND ADDRESSING MODES 82
5PERIPHERALS.........................................................84
5.1 CLOCKGENERATOR ..............................................84
5.1.1 ST72251 Miscellaneous Register ..........................................84
5.1.2 ST72311 Miscellaneous Register ..........................................85
5.2 INTERRUPT PROCESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
5.2.1 Interruptsourcesandinterruptvectors......................................86
5.2.1.1 InterruptssourcesfortheST72251 ....................................87
5.2.1.2 InterruptsourcesfortheST72311.....................................88
5.2.2 Interruptvectorization ...................................................89
5.2.3 Globalinterruptenablebit................................................90
5.2.4 TRAPinstruction.......................................................91
5.2.5 Interrupt mechanism ....................................................91
5.2.5.1 Savingtheinterruptedprogramstate ..................................91
5.2.5.2 Interruptserviceroutine.............................................91
5.2.5.3 Restoringtheinterruptedprogramstate:TheIRETinstruction ...............92
5.2.6 Nestingtheinterruptservices .............................................92
5.3 PARALLELINPUT-OUTPUTPORTS ..................................94
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